By Jayashankar Narayanankutty, Group Director, Cadence Design Systems
As we are ushered into a future brimming with digital complexity, it’s become exceedingly clear that the lifeblood of this new era is pumped by one crucial industry: semiconductors. From smartphones to servers underpinning the cloud, semiconductor chips are indispensable in our march toward an increasingly tech-dependent reality. One common thing in most devices around us is that the real estate available on them for specific workloads is getting smaller, and devices must run multiple workloads optimally.
This can only be achieved by integrating as many functions as possible into a system-on-chip (SoC), making them smaller and more reliable. The industry has followed Moore’s law for decades to meet such demands by reducing transistor sizes. However, with artificial intelligence (AI) /machine language (ML) and high-performance computing (HPC), the demand for compute performance and data transfer for hyperscale data centres is at an all-time high.
The chip manufacturers are facing technological and economic challenges at advanced nodes, and there has been a need to find innovative solutions and achieve performance improvements with reduced power. Stacking chips in the same package (3D) and a multi-chiplet system with a silicon interposer on the same package (2.5D) are emerging as solutions. By using advanced interconnect technology to combine hardened IP blocks or specialised chiplets, engineers can avoid the compounding issues of extreme transistor shrinkage, such as increased defect rates and overheating.
The rise of Chiplets in semiconductor design: Key drivers
Chiplets aren’t just the next step but a significant leap in semiconductor design philosophy. They offer a compelling value proposition by enabling unprecedented density and performance improvements without the downsides typically associated with traditional miniaturization approaches. As pivotal elements in various industries, chiplets are anticipated to be crucial in developing mobile and automotive technologies, data centers, AI processing, and more. They are vital in sectors demanding high-density and high-performance chip architectures—such as networking, AI/ML, real-time analytics, and media processing—making chiplets an optimal solution. Designing with chiplets offers numerous benefits such as:
Optimised Design Efficiency: All workloads are not equal. Chiplets offer the opportunity to precisely tailor products by selecting the best-suited process nodes for required functionalities.
This leads to reduced fault ratios, improved yield, and cost benefits.
Expedited Time-to-market: All functionalities are not equal; chiplets shorten the design cycles and allow the designers to concentrate on their secret sauce. The smaller dies in chiplets also reduce defect opportunities.
Unprecedented flexibility: The chiplet architecture empowers chip makers to leverage the most appropriate advanced node for specific functions, avoiding the risks and costs associated with an entire die shrink.
Challenges and solutions
The heterogeneous chiplet integration market is experiencing rapid growth and is being dominated by several key players. These players include zGlue Inc., Advanced Micro Devices (AMD), Intel Corp., Marvell Technology Group, Netronome, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC), NHanced Semiconductors, Inc., and NXP Semiconductors.
However, as we embark on an intricate journey with the development of SoC design using chiplets and making it readily available to the masses, there are some tribulations, and the industry is making good progress in resolving them. For instance, twelve leading companies from Japan, comprising automotive, electrical component, and semiconductor manufacturers, have set up the ‘Advanced SoC Research for Automotive’ (ASRA) to research and develop SoCs for automobiles using chiplet technology. One of the most critical challenges is establishing industry-wide standardisation to ensure interoperability between chiplets from different vendors.
Currently, there are multiple standards, like NVLink, Infinity fabric, Qlink, AIB, etc. However, it is crucial to have interoperability between chiplets from different manufacturers to design a custom IC. Fortunately, the industry is making progress in resolving these challenges, and the Universal Chiplet Interconnect Express (UCIe) is an open-source standard that is bringing about a change.
Evaluating multiple chiplets and integrating them into a cohesive unit is a complex task that requires careful consideration of various aspects that may affect performance. These aspects include compatibility, coherency, heat dissipation, and power consumption. The industry’s commitment to overcoming obstacles is reflected in developing new standards and algorithms, such as UCIe and bespoke testing protocols. These advancements are crucial to ensure seamless interfacing of chiplets within a system and to maintain system
integrity and performance. The possible disaggregated nature of chiplets in the future means multiple stakeholders will be involved, possibly leading to coordination problems, increased lead times, and inventory management problems.
Such inefficiencies in the supply chain can stunt innovation in this sector and must be addressed. To overcome these challenges, it is vital to rethink supply chains from a linear to a more networked and agile model, where data transparency and real-time communication are at the core of operations. By forging strategic partnerships and utilising intelligent technologies such as AI and blockchain for supply chain management, we can herald a new era of efficiency and collaboration in 3D IC design with chiplets.
Also, ensuring the modular components work together without introducing vulnerabilities is paramount in today’s age of perpetually evolving cyber threats. While some considerations may apply to the use of externally sourced IP blocks in homogeneous dies, the lack of visibility into a chiplet, a hardened IP, makes it more challenging to identify and mitigate vulnerabilities. Ensuring these modular components can work together seamlessly without introducing any security risks is essential.
Future of Chiplets
3D-IC technology is still in its early stages, but it is expected to gain momentum in the upcoming years as more companies invest in its development. This technology has the potential to revolutionise the semiconductor industry and pave the way for the creation of innovative products in the future. By embracing Chiplets and 3D-ICs, companies will gain a competitive edge in this dynamic landscape. It is not just a choice but a strategic imperative to look forward to the future of electronic design with exciting possibilities.
The impetus for chiplets-based solutions escalates as we witness the boom in connected devices. Industries are now facing the challenge of providing ultra-responsive and real-time services in smaller form factors, which chiplets can handle effectively. The rapid growth of the heterogeneous chiplet integration market is not just speculation but is backed by significant strategic investments in initiatives like the US CHIPS Act.
This act aims to make the US a semiconductor research and packaging innovation leader. Cloud computing, IoT, and edge computing trends highlight the need for the agility and performance that chiplet designs offer, setting the stage for this groundbreaking trend in semiconductor design. Gartner’s forecast of a 16.8% growth in the semiconductor industry by 2024 proves the enduring demand for technologies such as Generative AI, HPC, and edge computing. These technologies require vast computing capabilities, high bandwidth, and low latency.